This invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device provided with a plurality of power supply terminals.
In recent years, in semiconductor integrated circuit devices, the chip size is increasing with enlargement of the circuit scale, and noise of the power supply voltage V.sub.CC or the power supply voltage V.sub.SS is increasing with the higher speed data access provided. In order that such noise does not have a bad influence on the circuit operation, there is the tendency for the number of power supply terminals to be increased in the future.
A conventional device provided with a plurality of power supply terminals will now be described by taking the example of a dynamic memory.
The circuit configuration of the cell array and the sense amplifier corresponding to the center portion of the dynamic memory is shown in FIG. 3. As shown in this figure, memory cells are arranged in the form of a matrix having m rows and n columns, and respective memory cells are selected by word lines WL1 to WLn. Thus, data are read out from bit line pairs BL1 to BLm, BL1 to BLm. For example, a memory cell in the first row, the first column is comprised of an N-channel transistor 501 and a capacitor 511, wherein the drain is connected to the bit line BL1, and the gate is connected to the word line WL1. Furthermore, the drain of an N-channel transistor 521 constituting a memory cell together with a capacitor 531 is connected to, e.g., the other bit line BL1 of the bit line pair, and the gate is connected to the word line WLn.
Data of memory cells selected by word lines WL1 to WLn are sensed and amplified by N-channel sense amplifiers and P-channel sense amplifiers provided for every bit line pair. For example, the drain and the gate of an N-channel transistor 541 and the gate and the drain of an N-channel transistor 551 are respectively connected to bit line pairs BL1, BL1 wherein these N-channel transistors 541 and 551 constitute an N-channel sense amplifier. Furthermore, the source and the gate of a P-channel transistor 561 and the gate and the source of a P-channel transistor 571 are similarly respectively connected to the bit line pairs BL1, BL1 wherein these P-channel transistors constitute a P-channel sense amplifier. In addition, the common source of the N-channel transistors 541 and 551 is connected to a signal line L.sub.SAN, and the common drain of the P-channel transistors 561 and 571 is connected to a signal line L.sub.SAP.
The operation of the memory cell and the sense amplifier thus constructed will now be described with reference to FIG. 4 showing waveforms of respective signals. For example, the word line WL1 is selected, data stored in a memory cell 501 is transferred to a bit line. An N-channel sense amplifier driver (not shown) becomes operative, so the signal line L.sub.SAN is caused to be at low level. Thus, a potential V52 which is a lower one of potentials on the bit line pairs begins to be further lowered. At this time, since charges stored in the capacitor of the bit line BL1 or BL1, which is a lower one of potentials on the bit lines BL1 and BL1, are discharged to the power supply voltage V.sub.SS side, current flows into the power supply voltage V.sub.SS side, this power supply voltage V.sub.SS is caused to be in a floating state, giving rise to positive noise.
When a P-channel sense amplifier driver (not shown) becomes operative so that the potential on the signal line L.sub.SAP is caused to be at high level, a potential V51 which is a higher one of potentials on the bit line pairs BL1 and BL1 begins to rise. In this case, since charging is carried out by the capacitor which is the higher one of the potentials on the bit line pairs BL1 and BL1 a current flows into the power supply voltage V.sub.CC side, so noise is generated in this voltage.
When the sense amplifier becomes operative in this way, noise is produced in the power supply voltage V.sub.SS, and the operating margin of the external input circuit is lowered. To the initial stage of the external input circuit, the circuit as shown in FIG. 5 is connected. Between an input terminal 403 connected to the circuit outside the chip and an output terminal 404 connected to the circuit of the succeeding stage, an inverter comprised of a P-channel transistor 401 and an N-channel transistor 402 are connected.
Generally, such an inverter circuit is used in the state connected to a TTL logic element. For this reason, setting of the threshold value of the logic level is ordinarily made such that a voltage of more than 2.4 volts is assumed as a high level, and a voltage less than 0.8 volts is assumed as a low level. In view of this, the circuit threshold value of the inverter shown in FIG. 5 is set to 1.6 volts.
Assuming now that the V.sub.CC power supply provided in the vicinity of such an inverter is affected by noise of +0.6 volts, the circuit threshold value of this inverter rises from 1.6 volts up to 2.2 volts. In the case where there is no noise, when a voltage of more than 1.6 volts is input, this voltage is considered as a high level, so the inverter outputs a signal of low level. However, in order to output such a signal of low level in the case where noise is produced, a voltage of more than 2.2 volts is required because the circuit threshold value rises up to 2.2 volts as described above. Accordingly, with respect to 2.4 volts prescribing high level, although there is a margin of 0.8 volts in the case where there is no noise, the margin is reduced to 0.2 volts in the case where noise is produced. This is the same also in connection with an input signal of low level having 0.8 volts as a prescribed value.
Conversely, when the V.sub.SS power supply in the vicinity with this inverter is affected by noise of -0.6 volts, the circuit threshold value is lowered from 1.6 volts down to 1.0 volt. Thus, while when an input voltage of less than 1.6 volts is input in the case where there is no noise, this input voltage is considered as a low level, in the case where the inverter circuit is affected by noise, it is required that an input voltage be less than 1.0 volts. Namely, with respect to 0.8 volts prescribing low level, a margin of 0.8 volts is originally provided. However, the margin is reduced to 0.2 volts with the occurrence of such noise of -0.6 volts. Also in this case, the margin is similarly lowered with respect to a signal of high level having 2.4 volts as a prescribed value, leading to erroneous operation.